Hiseeu 5MP PTZ gk7605v100 sc223a

Sensor

Camera needs _4l driver, got it from telegram channel. Source? config as follows:

• /etc/sensors/sc223a_4l_i2c_1080p.ini

[sensor]
Sensor_type=stSnsSc223aObj
Mode=WDR_MODE_NONE
DllFile=libsns_sc223a_4l.so

[mode]
input_mode=INPUT_MODE_MIPI
raw_bitness=10

[mipi]
lane_id = 0|1|-1|-1|-1|-1|-1|-1|      ;lane_id: -1 - disable

[isp_image]
Isp_FrameRate=30
Isp_Bayer=BAYER_BGGR

[vi_dev]
Input_mod=VI_MODE_MIPI
Work_mod =0     ;VI_WORK_MODE_1Multiplex = 0
                ;VI_WORK_MODE_2Multiplex,
                ;VI_WORK_MODE_4Multiplex
Combine_mode =0 ;Y/C composite or separation mode
                ;VI_COMBINE_COMPOSITE = 0 /*Composite mode */
                ;VI_COMBINE_SEPARATE,     /*Separate mode */
Comp_mode    =0 ;Component mode (single-component or dual-component)
                ;VI_COMP_MODE_SINGLE = 0, /*single component mode */
                ;VI_COMP_MODE_DOUBLE = 1, /*double component mode */
Clock_edge   =1 ;Clock edge mode (sampling on the rising or falling edge)
                ;VI_CLK_EDGE_SINGLE_UP=0, /*rising edge */
                ;VI_CLK_EDGE_SINGLE_DOWN, /*falling edge */
Mask_num     =2 ;Component mask
Mask_0       =0xFFF00000
Mask_1       =0x0
Scan_mode    = 1;VI_SCAN_INTERLACED = 0
                ;VI_SCAN_PROGRESSIVE,
Data_seq     =2 ;data sequence (ONLY for YUV format)
                ;----2th component U/V sequence in bt1120
                ;    VI_INPUT_DATA_VUVU = 0,
                ;    VI_INPUT_DATA_UVUV,
                ;----input sequence for yuv
                ;    VI_INPUT_DATA_UYVY = 0,
                ;    VI_INPUT_DATA_VYUY,
                ;    VI_INPUT_DATA_YUYV,
                ;    VI_INPUT_DATA_YVYU

Vsync   =1      ; vertical synchronization signal
                ;VI_VSYNC_FIELD = 0,
                ;VI_VSYNC_PULSE,
VsyncNeg=1      ;Polarity of the vertical synchronization signal
                ;VI_VSYNC_NEG_HIGH = 0,
                ;VI_VSYNC_NEG_LOW /*if VIU_VSYNC_E
Hsync  =0       ;Attribute of the horizontal synchronization signal
                ;VI_HSYNC_VALID_SINGNAL = 0,
                ;VI_HSYNC_PULSE,
HsyncNeg =0     ;Polarity of the horizontal synchronization signal
                ;VI_HSYNC_NEG_HIGH = 0,
                ;VI_HSYNC_NEG_LOW
VsyncValid =1   ;Attribute of the valid vertical synchronization signal
                ;VI_VSYNC_NORM_PULSE = 0,
                ;VI_VSYNC_VALID_SINGAL,
VsyncValidNeg =0;Polarity of the valid vertical synchronization signal
                ;VI_VSYNC_VALID_NEG_HIGH = 0,
                ;VI_VSYNC_VALID_NEG_LOW
Timingblank_HsyncHfb =0     ;Horizontal front blanking width
Timingblank_HsyncAct =1920  ;Horizontal effetive width
Timingblank_HsyncHbb =0     ;Horizontal back blanking width
Timingblank_VsyncVfb =0     ;Vertical front blanking height
Timingblank_VsyncVact =1080  ;Vertical effetive width
Timingblank_VsyncVbb=0      ;Vertical back blanking height
Timingblank_VsyncVbfb =0    ;Even-field vertical front blanking height(interlace, invalid progressive)
Timingblank_VsyncVbact=0    ;Even-field vertical effetive width(interlace, invalid progressive)
Timingblank_VsyncVbbb =0    ;Even-field vertical back blanking height(interlace, invalid progressive)
InputDataType=1 ;VI_DATA_TYPE_YUV = 0,VI_DATA_TYPE_RGB = 1,
DataRev      =FALSE ;Data reverse. FALSE = 0; TRUE = 1
DevRect_x=200
DevRect_y=20
DevRect_w=1920
DevRect_h=1080

uart

• ./general/package/all-patches/linux/9000-enable-uart1.patch

--- a/arch/arm/boot/dts/gk7605v100-demb.dts       2023-08-09 13:43:00.715983714 +0200
+++ b/arch/arm/boot/dts/gk7605v100-demb.dts       2023-08-09 13:42:25.609040743 +0200
@@ -20,7 +20,7 @@
 };

 &uart1 {
-       status = "disabled";
+       status = "okay";
 };

 &uart2 {

ipctool reginfo | grep UART

devmem 0x112c0078 32 0x01
devmem 0x112c007c 32 0x01

reflash kernel via uboot

## does not work?
setenv ipaddr 192.168.1.10; setenv serverip 192.168.1.11
setenv flash_addr 0x50000
setenv uimage_size 0x300000

mw.b ${baseaddr} 0xff 0x1000000
tftpboot ${baseaddr} uImage
sf probe 0; sf lock 0;

sf erase ${flash_addr} ${uimage_size}
sf write ${loadaddr} ${flash_addr} ${filesize}
original:

uknor16m=mw.b ${baseaddr} ff 1000000; tftpboot ${baseaddr} uImage.${soc} && sf probe 0; sf erase 0x50000 0x300000; sf write ${baseaddr} 0x50000 ${filesize}
urnor16m=mw.b ${baseaddr} ff 1000000; tftpboot ${baseaddr} rootfs.squashfs.${soc} && sf probe 0; sf erase 0x350000 0xa00000; sf write ${baseaddr} 0x350000 ${filesize}